Generally, a charge pump is used to generate an internal voltage, e.g., 2VDD or 4VDD, which is higher than a supply voltage VDD. A Dickson charge pump is widely used as the charge pump.
FIG. 1 is a circuit diagram of a general Dickson charge pump.
As shown in FIG. 1, a first input clock signal IN1 and a second input clock signal IN2 are inputted through inverters, and the first and second input clock signals IN1 and IN2 swing with swing amplitude of VDD. The first input clock signal IN1 is out of phase with the second input clock signal IN2. That is, the second input clock signal IN2 is generated by inverting the first input clock signal IN1.
The Dickson charge pump includes a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, a first flying capacitor C1, and a second flying capacitor C2.
In the first NMOS transistor N1, a drain is coupled to the supply voltage VDD, a source is connected to a node VA, and a gate is connected to a node VB. In the second NMOS transistor N2, a drain is coupled to the supply voltage VDD, a source is connected to the node VB, and a gate is connected to the node VA.
In the first PMOS transistor P1, a source is connected to the node VA, a drain is connected to an output voltage terminal Vout, and a gate is connected to the node VB. In the second PMOS transistor P2, a source is connected to the node VB, a drain is connected to the output voltage terminal Vout, and a gate is connected to the node VA.
The first flying capacitor C1 is connected between the node VA and a first clock input terminal IN1. The second flying capacitor C2 is connected between the node VB and a second input clock terminal IN2.
A load capacitor CL connected between the output voltage terminal Vout and a ground terminal GND. The load capacitor CL is formed by modeling a load capacitance.
FIG. 2 is a diagram showing waveforms at each node of the Dickson charge pump shown in FIG. 1. Hereinafter, operations of the Dickson charge pump will be described referring to FIG. 2.
When a voltage level of a node IN1 is VDD and a voltage level of a node IN2 is GND, a voltage level of the node VA is raised to 2VDD due to a bootstrapping phenomenon. Then, the second NMOS transistor N2 is turn-on, charges the second flying capacitor C2, and thus a voltage level of the node VB becomes VDD. Then, the second PMOS transistor P2 and the first NMOS transistor N1 are turn-off due to the node VB having the VDD, the first PMOS transistor P1 is turn-on and a voltage level of the node VA becomes 2VDD. Consequently, the load capacitor CL connected to the output voltage terminal Vout is charged with 2VDD.
When a voltage level of the node IN1 is GND and a voltage level of the node IN2 is VDD, the voltage level of the node VB having VDD is raised to 2VDD due to the bootstrapping phenomenon. Then, the first NMOS transistor N1 is turn-on, charges the first flying capacitor C1, and thus a voltage level of the node VA becomes VDD. Then, the first PMOS transistor P1 and the second NMOS transistor N2 are turn-off due to the node VA having the VDD level, the second PMOS transistor P2 is turn-on and a voltage level of the node VB becomes 2VDD. Consequently, the load capacitor CL connected to the output voltage terminal Vout is charged with 2VDD.
In other words, when the voltage level of the node VA is 2VDD, the first NMOS transistor N1 is turn-off, the first PMOS transistor P1 is turn-on, the output voltage terminal Vout becomes 2VDD and the node VB is charged with VDD. When the voltage level of the node VB is 2VDD, the second NMOS transistor N2 is turn-off, the second PMOS transistor P2 is turn on, the output voltage terminal Vout becomes 2VDD and the node VA is charged with VDD. Voltage levels of the node VA and the node VB are alternatively raised to 2VDD, the raised voltage charges the load capacitor CL and the output voltage is constantly 2VDD.
The Dickson charge pump is a basic charge pump. The Dickson charge pump generates 2VDD output voltage from the supply voltage VDD by receiving the out-of phase clock signals without a separated controller.
FIG. 3 is a circuit diagram of a general level shifter.
As shown in FIG. 3, the level shifter is a circuit for transforming swing amplitude of the clock signal. The level shifter transforms the first input clock signal IN1 having VDD swing amplitude into a third input clock signal IN3 having 2VDD swing amplitude, and outputs the third input clock signal to a output terminal OUT1.
The level shifter includes a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3 and a fourth NMOS transistor N4.
In the third PMOS transistor P3, a source is coupled to a second supply voltage VDD2, a drain is connected to a node VC, and a gate is connected to the first output terminal OUT1. In the fourth PMOS transistor P4, a source is coupled to the second supply voltage VDD2, a drain is connected to the first output terminal OUT1, and a gate is connected to the node VC.
In the third NMOS transistor N3, a source is connected to the first clock input terminal IN1, a drain is connected to the node VC, and a gate is coupled to the supply voltage VDD. In the fourth NMOS transistor N4, a source is connected to the GND, a drain is connected to the first output terminal OUT1, and a gate is connected to the first clock input terminal IN1.
FIG. 4 is a diagram showing waveforms at each node of the level shifter shown in FIG. 3. Hereinafter, operations of the level shifter will be described referring to FIG. 4.
When a voltage level of the first input clock signal IN1 is VDD, the fourth NMOS transistor N4 is turn-on and a voltage level of the first output terminal OUT1 is GND. Then, the third PMOS transistor P3 becomes turn-on and the fourth PMOS transistor P4 becomes turn-off due to cross-coupled structure.
On the other hand, when the voltage level of the first input clock signal IN1 is GND, the fourth NMOS transistor N4 is turn-off, the third NMOS transistor N3 becomes turn-on and the fourth PMOS transistor P4 becomes turn-on. Then, when the fourth PMOS transistor P4 is turn-on, third PMOS transistor P3 is turn-off, the third PMOS transistor P3 prevents current flows through the third NMOS transistor N3, and the first output terminal OUT1 becomes VDD2 due to the cross-coupled structure.
As described above, while the first input clock signal swings between VDD and GND, the first output terminal OUT1 swings between GND and the second supply voltage VDD2 in the level shifter.
FIG. 5 is a circuit diagram of a cascade charge pump receiving the supply voltage VDD and generating 4VDD, which is quadruple of the supply voltage. The cascade charge pump is formed by cascading the Dickson charge pump and the level shifter.
As shown in FIG. 5, the cascade charge pump is formed by connecting two Dickson charge pumps 100 and 200 by using the level shifter 300. The Dickson charge pump is called as a cross-coupled doubler.
Structure of each Dickson charge pump 100 and 200 is the same as that of Dickson charge pump shown in FIG. 1, and the detailed description will be omitted.
FIG. 6 is a diagram showing waveforms at each node of the cascade charge pump shown in FIG. 5. Hereinafter, operations of the cascade charge pump will be described referring to FIG. 6.
The cascade charge pump includes a first Dickson charge pump 100, a second Dickson charge pump 200 and the level shifter 300.
The first Dickson charge pump 100 is the same as the Dickson charge pump shown in FIG. 1. That is, the first Dickson charge pump 100 receives input clock signals IN1 and IN2 which are out-of phase for each other and swing between GND and VDD, and generates IN1′ and IN2′ swing between VDD and 2VDD by using flying capacitors C3 and C4. A voltage level of the first output terminal Vout1 is raised to 2VDD by repeatedly outputting IN1′ and IN2′ having 2VDD.
An output voltage of the first Dickson charge pump 100 is used as a power source of the second Dickson charge pump 200 and the level shifter 300. The level shifter 300 receives the output voltage 2VDD of the first Dickson charge pump 100 and the first input clock signal IN1, generates a signal OUT1 having 2VDD swing amplitude, and outputs the signal OUT1 to the second Dickson charge pump 200. The signal OUT1 is inputted to the second Dickson charge pump 200 as a third input clock signal IN3 and a fourth input clock signal IN4 through inverters.
Accordingly, the second Dickson charge pump 200 uses output voltage 2VDD of the first Dickson charge pump 100 as the power source and receives the signal OUT1 having 2VDD swing amplitude from the level shifter 300 as an input signal. Then, the second Dickson charge pump 200 generates a signal IN3′ and a signal IN4′ swing between 2VDD and 4VDD by using flying capacitors C5 and C6. Herein, a voltage level of a second output terminal Vout2 is raised to 4VDD by repeatedly outputting IN3′ and IN4′ having 4VDD.
As described above, the conventional high-voltage CMOS charge pump requires two charge pumps, one level shifter, and four inverters in order to raise the supply voltage VDD up to the quadruple 4VDD of the supply voltage. Therefore, a large layout area is needed to implement the conventional high-voltage CMOS charge pump having a lot of MOS transistors.